Integer Store Operations for Streaming SIMD Extensions 2

The following store operation intrinsics and their respective instructions are functional in the Streaming SIMD Extensions 2 (SSE2).

The detailed description of each intrinsic contains a table detailing the returns. In these tables, p is an access to the result.

The prototypes for SSE2 intrinsics are in the emmintrin.h header file.

Intrinsic Name Operation Corresponding SSE2 Instruction
_mm_stream_si128 Store MOVNTDQ
_mm_stream_si32 Store MOVNTI
_mm_store_si128 Store MOVDQA
_mm_storeu_si128 Store MOVDQU
_mm_maskmoveu_si128 Conditional store MASKMOVDQU
_mm_storel_epi64 Store lowest MOVQ

 

void _mm_stream_si128(__m128i *p, __m128i a)

Stores the data in a to the address p without polluting the caches. If the cache line containing address p is already in the cache, the cache will be updated. Address p must be 16 byte aligned.

*p
a

 

void _mm_stream_si32(int *p, int a)

Stores the data in a to the address p without polluting the caches. If the cache line containing address p is already in the cache, the cache will be updated.

*p
a

 

void _mm_store_si128(__m128i *p, __m128i b)

Stores 128-bit value. Address p must be 16 byte aligned.

*p
a

 

void _mm_storeu_si128(__m128i *p, __m128i b)

Stores 128-bit value. Address p need not be 16-byte aligned.

*p
a

 

void _mm_maskmoveu_si128(__m128i d, __m128i n, char *p)

Conditionally store byte elements of d to address p. The high bit of each byte in the selector n determines whether the corresponding byte in d will be stored. Address p need not be 16-byte aligned.

if (n0[7]) if (n1[7] ... if (n15[7])
p[0] := d0 p[1] := d1 ... p[15] := d15

 

void _mm_storel_epi64(__m128i *p, __m128i a)

Stores the lower 64 bits of the value pointed to by p.

*p[63:0]
a0