The following load operation intrinsics and their respective instructions are functional in the Streaming SIMD Extensions 2 (SSE2).
For detailed information about an intrinsic, click on that intrinsic name in the following table.
The results of each intrinsic operation are placed in registers. The information about what is placed in each register appears in the tables below, in the detailed explanation of each intrinsic. R, R0 and R1 represent the registers in which results are placed.
The prototypes for SSE2 intrinsics are in the emmintrin.h header file.
| Intrinsic Name | Operation | Instruction |
|---|---|---|
| mm_load_si128 | Load | MOVDQA |
| _mm_loadu_si128 | Load | MOVDQU |
| _mm_loadl_epi64 | Load and zero | MOVQ |
__m128i _mm_load_si128(__m128i const*p)
Loads 128-bit value. Address p must be 16-byte aligned.
| R |
|---|
| *p |
__m128i _mm_loadu_si128(__m128i const*p)
Loads 128-bit value. Address p not need be 16-byte aligned.
| R |
|---|
| *p |
__m128i _mm_loadl_epi64(__m128i const*p)
Load the lower 64 bits of the value pointed to by p into the lower 64 bits of the result, zeroing the upper 64 bits of the result.
| R0 | R1 |
|---|---|
| *p[63:0] | 0x0 |